The present invention relates generally to flash memory devices, and more particularly, to a method for forming STI (shallow trench isolation) structures within the core and periphery areas of a flash memory device with rounding at corners of the semiconductor substrate adjacent the STI structures and with preservation of the integrity of the tunnel dielectric of the core flash memory cells.
Referring to FIG. 1, a flash memory cell 100 of a flash memory device includes a tunnel dielectric 102 typically comprised of silicon dioxide (SiO2) or nitrided oxide as known to one of ordinary skill in the art of integrated circuit fabrication. The tunnel dielectric 102 is disposed on a core active device area 103 of a semiconductor substrate or a p-well. In addition, a floating gate 104, comprised of a conductive material such as polysilicon for example, is disposed over the tunnel dielectric 102. A floating dielectric 106, typically comprised of silicon dioxide (SiO2) or ONO (a sandwich of oxide-nitride-oxide, as known to one of ordinary skill in the art of integrated circuit fabrication), is disposed over the floating gate 104. A control gate 108, comprised of a conductive material such as polysilicon, is disposed over the floating dielectric 106.
A drain bit line junction 110 that is doped with a junction dopant, such as arsenic (As) or phosphorous (P) for example, is formed within the core active device area 103 of the semiconductor substrate or p-well toward a left sidewall of the floating gate 104 in FIG. 1. A source bit line junction 114 that is doped with the junction dopant is formed within the core active device area 103 of the semiconductor substrate or p-well 106 toward a right sidewall of the floating gate 104 of FIG. 1. The core active device area 103 is defined by surrounding STI (shallow trench isolation) structures 109 comprised of an insulating material such as silicon dioxide (SiO2) for example. Such a flash memory cell 100 comprising a flash memory device is known to one of ordinary skill in the art of integrated circuit fabrication.
During the program or erase operations of the flash memory cell 100 of FIG. 1, charge carriers are injected into or injected out of the floating gate 104. Such variation of the amount of charge carriers within the floating gate 104 alters the threshold voltage of the flash memory cell 100, as known to one of ordinary skill in the art of flash memory technology. For example, when electrons are the charge carriers that are injected into the floating gate 104, the threshold voltage increases. Alternatively, when electrons are the charge carriers that are injected out of the floating gate 104, the threshold voltage decreases. These two conditions are used as the two states for storing digital information within the flash memory cell 100, as known to one of ordinary skill in the art of electronics.
During programming of the flash memory cell 100 for example, a voltage of +9 Volts is applied on the control gate 108, a voltage of +5 Volts is applied on the drain bit line junction 110, and a voltage of 0 Volts is applied on the source bit line junction 114 and on the semiconductor substrate or p-well 103. With such bias, when the flash memory cell 100 is an N-channel flash memory cell, electrons are injected into the floating gate 104 to increase the threshold voltage of the flash memory cell 100 during programming of the flash memory cell 100.
Alternatively, during erasing of the flash memory cell 100, a voltage of xe2x88x929.5 Volts is applied on the control gate 108, a voltage of 0 Volts is applied on the drain bit line junction 110, and a voltage of +4.5 Volts is applied on the source bit line junction 114 and on the semiconductor substrate or p-well 103 for example. With such bias, when the flash memory cell 100 is an N-channel flash memory cell, electrons are pulled out of the floating gate 104 to decrease the threshold voltage of the flash memory cell 100 during erasing of the flash memory cell 100. Such an erase operation is referred to as an edge erase process by one of ordinary skill in the art of flash memory technology.
In an alternative channel erase process, a voltage of xe2x88x929.5 Volts is applied on the control gate 108 and a voltage of +9 Volts is applied on the semiconductor substrate or p-well 103 with the drain and source bit line junctions 110 and 114 floating. With such bias, when the flash memory cell 100 is an N-channel flash memory cell, electrons are pulled out of the floating gate 104 to the substrate or p-well 103 to decrease the threshold voltage of the flash memory cell 100 during erasing of the flash memory cell 100.
FIG. 2 illustrates an example semiconductor die 150 having a flash memory device fabricated thereon. The flash memory device includes a core area 152 having an array of flash memory cells fabricated thereon and a periphery area 154 having logic circuitry fabricated thereon, as known to one of ordinary skill in the art of flash memory devices. FIG. 3 illustrates the array of flash memory cells fabricated in the core area 152, as known to one of ordinary skill in the art of flash memory technology. Referring to FIG. 3, the array of flash memory cells 200 includes rows and columns of flash memory cells with each flash memory cell having similar structure to the flash memory cell 100 of FIG. 1. The array of flash memory cells 200 of FIG. 3 is illustrated with 2 columns and 2 rows of flash memory cells for simplicity and clarity of illustration. However, a typical array of flash memory cells comprising an electrically erasable and programmable memory device has more numerous rows and columns of flash memory cells such as 512 rows and 512 columns of flash memory cells for example.
Further referring to FIG. 3, in the array of flash memory cells 200, the control gate terminals of all flash memory cells in a row of the array are coupled together to form a respective word line for that row. In FIG. 3, the control gate terminals of all flash memory cells in the first row are coupled together to form a first word line 202, and the control gate terminals of all flash memory cells in the second row are coupled together to form a second word line 204. In addition, the drain terminals of all flash memory cells in a column are coupled together to form a respective bit line for that column. In FIG. 3, the drain terminals of all flash memory cells in the first column are coupled together to form a first bit line 206, and the drain terminals of all flash memory cells in the second column are coupled together to form a second bit line 208. Further referring to FIG. 3, the source terminal of all flash memory cells of the array 200 are coupled together to a source voltage VSS, and the substrate or p-well terminal of all flash memory cells of the array 200 are coupled together to a substrate voltage VSUB.
Referring to FIGS. 2 and 4, the logic circuitry of the periphery area 154 is comprised of conventional MOSFETs (metal oxide semiconductor field effect transistor) 250. The conventional MOSFET 250 includes a gate dielectric 252 typically comprised of silicon dioxide (SiO2) formed over a periphery active device area 254 of a semiconductor substrate or a p-well. In addition, a gate structure 256, comprised of a conductive material such as polysilicon, is disposed over the gate dielectric 252.
A drain junction 258 that is doped with a junction dopant, such as arsenic (As) or phosphorous (P) for example, is formed within the active device area 254 of the semiconductor substrate or p-well toward a left sidewall of the gate structure 256. A source junction 260 that is doped with the junction dopant is formed within the active device area 254 of the semiconductor substrate or p-well toward a right sidewall of the gate structure 256. The periphery active device area 254 is defined by surrounding STI (shallow trench isolation) structures 262 comprised of an insulating material such as silicon dioxide (SiO2) for example. Such a structure of the conventional MOSFET 250 comprising the logic circuitry of the periphery area 154 is known to one of ordinary skill in the art of integrated circuit fabrication.
Referring to FIG. 1, top corners 120 of the core active device area 103 are adjacent the first STI structures 109 surrounding the core active device area 103. Similarly, referring to FIG. 4, top corners 264 of the periphery active device area 254 are adjacent the second STI structures 262 surrounding the periphery active device area 254. During operation of the flash memory cell 100 and the MOSFET 250, relatively high voltages may be applied on the drain and source bit line junctions 110 and 114 of the flash memory cell 100 and on the drain and source junctions 258 and 260 of the MOSFET 250. With such high voltages, a higher leakage current undesirably flows through the drain and source bit line junctions 110 and 114 of the flash memory cell 100 when the top corners 120 of the core active device area 103 adjacent the first STI structures 109 are sharper corners. Similarly, with such high voltages, a higher leakage current undesirably flows through the drain and source junctions 258 and 260 of the MOSFET 250 when the top corners 264 of the periphery active device area 254 adjacent the second STI structures 262 are sharper corners.
Thus, a mechanism is desired for forming STI structures within the core area and within the periphery area with rounded top corners of the core active device area 103 and the periphery active device area 254 to minimize undesired leakage current.
Accordingly, in a general aspect of the present invention, STI structures are formed surrounding a core active device area and a periphery active device area of a flash memory device with rounded corners of the core active device area and the periphery active device area to minimize undesired leakage current.
In one embodiment of the present invention, STI (shallow trench isolation) structures are formed for a flash memory device fabricated within a semiconductor substrate comprised of a core area having an array of core flash memory cells fabricated therein and comprised of a periphery area having logic circuitry fabricated therein. A tunnel dielectric material is formed on the core area and the periphery area of the semiconductor substrate, and a first floating gate material is formed on the tunnel dielectric material of the core area and the periphery area of the semiconductor substrate. A first hardmask material is patterned to etch a first set of STI (shallow trench isolation) openings through the first floating gate material, the tunnel dielectric material, and the semiconductor substrate within the core area, and to etch a second set of STI (shallow trench isolation) openings through the first floating gate material, the tunnel dielectric material, and the semiconductor substrate within the periphery area. A core active device area of the semiconductor substrate within the core area is surrounded by the first set of STI openings, and a periphery active device area of the semiconductor substrate within the periphery area is surrounded by the second set of STI openings.
A dielectric liner is formed at sidewalls of the first and second sets of STI openings with reaction of the semiconductor substrate at the sidewalls of the STI openings such that corners of the semiconductor substrate of the core and periphery active device areas adjacent the STI openings are rounded. A trench dielectric material is deposited to fill the STI openings, and the first hardmask material is etched away. A second floating gate material is formed over any remaining portion of the first floating gate material and on the trench dielectric material within the core area and the periphery area. A second hardmask material is patterned to remain on the second floating gate material over the core active device area and over the whole periphery area. The second floating gate material exposed through the second hardmask material is etched away from the trench dielectric material within the core active device area.
The present invention may be used to particular advantage when the first floating gate material is comprised of an undoped semiconductor material such as undoped polysilicon such that the tunnel dielectric material adjacent the first floating gate material is not doped during formation of the dielectric liner at the sidewalls of the STI openings when the semiconductor substrate is heated to preserve the integrity of the tunnel dielectric material. In that case, the second floating gate material is comprised of doped semiconductor material such as doped polysilicon for enhanced conductivity of the floating gate and is deposited after formation of the dielectric liner of the STI openings to preserve the integrity of the tunnel dielectric material.
In a further embodiment of the present invention, spacers are formed on sidewalls of the second hardmask material disposed over the core active device area before the second floating gate material is etched such that the spacers are disposed over portions of the trench dielectric material adjacent the core active device area. In that case, the second floating gate material remains disposed over portions of the trench dielectric material adjacent the core active device area from being covered by the spacers of the second hardmask material.
In another embodiment of the present invention, the second hardmask material is etched away from the core area and the periphery area, and a floating gate dielectric material is formed on any exposed surfaces of the second floating gate material and the trench dielectric material within the core area and the periphery area. A masking material is patterned to remain on the floating gate dielectric material within the core area while exposing the floating gate dielectric material on the first and second floating gate materials within the periphery area. The floating gate dielectric material and the first and second floating gate materials within the periphery area are etched away to expose the semiconductor substrate of the periphery active device area and to expose the trench dielectric material filling the second set of STI openings within the periphery area. A dip-off etch of the trench dielectric material filling the second set of STI openings within the periphery area is performed to expose corners of the semiconductor substrate of the periphery active device area adjacent the second set of STI openings. A dummy dielectric is formed with the semiconductor substrate of the periphery active device area including the exposed corners of the periphery active device area adjacent the second set of STI openings. The dummy dielectric is etched from the semiconductor substrate for further rounding the exposed corners of the periphery active device area.
In this manner, the top corners of the core and periphery active device areas adjacent the STI structures are rounded for minimizing leakage current through a flash memory cell formed in the core active device area and through a MOSFET formed in the periphery active device area. In addition, the present invention may be used to particular advantage when the first floating gate material is comprised of an undoped semiconductor material such as undoped polysilicon such that the tunnel dielectric material adjacent the first floating gate material is not doped during formation of the dielectric liner at the sidewalls of the STI openings when the semiconductor substrate is heated to preserve the integrity of the tunnel dielectric material. In that case, the second floating gate material is comprised of doped semiconductor material such as doped polysilicon for enhanced conductivity of the floating gate and is deposited after formation of the dielectric liner of the STI openings to preserve the integrity of the tunnel dielectric material.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.